`include "defines.v"
/*-------------------------*/
/* Just to my beloved Rena */
/*-------------------------*/
module core(
  input clk,
  input rst_n,
  // 用户定义的可屏蔽中断 不影响核心运行的中断
  input user_interrupt,
  // 不可屏蔽的关键中断 例如 UPS断电信号 核心外设错误信号
  input sys_interrupt,
  /* boot  */
  input [`VADDR_W-1:0] boot_addr,
  /* AXI Master */
  /* AR  */
  input                               axi_ar_ready  ,
  output                              axi_ar_valid  ,
  output [`AXI_ADDR_WIDTH-1:0]        axi_ar_addr   ,
  output [2:0]                        axi_ar_prot   ,
  output [`AXI_ID_WIDTH-1:0]          axi_ar_id     ,
  output [`AXI_USER_WIDTH-1:0]        axi_ar_user   ,
  output [7:0]                        axi_ar_len    ,
  output [2:0]                        axi_ar_size   ,
  output [1:0]                        axi_ar_burst  ,
  output                              axi_ar_lock   ,
  output [3:0]                        axi_ar_cache  ,
  output [3:0]                        axi_ar_qos    ,
  /* R */
  output                              axi_r_ready   ,
  input                               axi_r_valid   ,
  input  [1:0]                        axi_r_resp    ,
  input  [`AXI_DATA_WIDTH-1:0]        axi_r_data    ,
  input                               axi_r_last    ,
  input  [`AXI_ID_WIDTH-1:0]          axi_r_id      ,
  input  [`AXI_USER_WIDTH-1:0]        axi_r_user    ,
  /* AW */
  input                               axi_aw_ready  ,       
  output                              axi_aw_valid  ,   
  output [`AXI_ADDR_WIDTH-1:0]        axi_aw_addr   ,   
  output [2:0]                        axi_aw_prot   ,   
  output [`AXI_ID_WIDTH-1:0]          axi_aw_id     ,
  output [`AXI_USER_WIDTH-1:0]        axi_aw_user   ,     
  output [7:0]                        axi_aw_len    ,      
  output [2:0]                        axi_aw_size   ,
  output [1:0]                        axi_aw_burst  ,
  output                              axi_aw_lock   ,   
  output [3:0]                        axi_aw_cache  ,   
  output [3:0]                        axi_aw_qos    ,   
  /* W */
  input                               axi_w_ready   ,  
  output                              axi_w_valid   ,
  output [`AXI_DATA_WIDTH-1:0]        axi_w_data    ,   
  output [`AXI_DATA_WIDTH/8-1:0]      axi_w_strb    ,   
  output                              axi_w_last    ,   
  /* B */
  output                              axi_b_ready   ,
  input                               axi_b_valid   ,
  input  [1:0]                        axi_b_resp    ,  
  input  [`AXI_ID_WIDTH-1:0]          axi_b_id      ,
  input  [`AXI_USER_WIDTH-1:0]        axi_b_user      
);
// fronted
wire ctrl_fronted_flush;
wire bru_fronted_misPredict;
wire bru_fronted_valid;
wire ctrl_baq_flush;
wire [`VADDR_W-1:0] bru_fronted_JumpOldPC;
wire [`VADDR_W-1:0] bru_fronted_misPrePC;
wire fronted_idu_valid;
wire idu_fronted_ready;
wire [31:0] fronted_idu_instr;
wire [`VADDR_W-1:0] fronted_idu_pc;
wire fronted_mem_addr_valid;
wire mem_fronted_data_valid;
wire [`PADDR_W-1:0] fronted_mem_addr;
wire [127:0] mem_fronted_data;
wire commit_fronted_exception  ;
wire [`VADDR_W-1:0]commit_fronted_exceptionPC;
wire                baq_bru_valid;
wire                bru_baq_ready;
wire [`VADDR_W-1:0] baq_bru_dout ;
wire fronted_idu_pre;
wire invalidateIcache;
// idu
wire ctrl_idu_flush;
wire isu_idu_ready;
wire idu_isu_valid;
wire [`FU_W-1:0]idu_isu_fu;
wire [`OP_W-1:0]idu_isu_op;
wire [4:0] idu_isu_rs1;
wire [4:0] idu_isu_rs2;
wire [4:0] idu_isu_rd;
wire idu_isu_rfwen;
wire [1:0]idu_isu_src1;
wire [1:0]idu_isu_src2;
wire [`XLEN-1:0]idu_isu_imm;
wire [`VADDR_W-1:0]idu_isu_pc;
wire [31:0] idu_isu_inst;
wire idu_isu_pre;
// isu
wire ctrl_isu_flush;
wire exu_isu_ready;
wire isu_exu_valid;
wire [`OP_W-1:0]isu_exu_op;
wire [4:0] isu_exu_rd;
wire isu_exu_rfwen;
wire [`XLEN-1:0] isu_exu_op1;
wire [`XLEN-1:0] isu_exu_op2;
wire [`XLEN-1:0] isu_exu_imm;
wire [`ADDR_W-1:0] isu_exu_pc;
wire alu_enable ;
wire aluw_enable;
wire bru_enable ;
wire csr_enable ;
wire lsu_enable ;
wire                 exu_isu_wen  ;  
wire [4:0]           exu_isu_addr ; 
wire [`XLEN-1:0]     exu_isu_data ; 
wire                 wbu_isu_wen  ; 
wire [4:0]           wbu_isu_addr ; 
wire [`XLEN-1:0]     wbu_isu_data ;
wire [31:0]          isu_exu_inst;
wire isu_exu_pre;
// exu
wire bru_fronted_brunch;
wire ctrl_exu_flush;
wire wbu_exu_ready ;
wire exu_wbu_valid; 
wire exu_wbu_wen;   
wire [4:0]         exu_wbu_rd;    
wire [`XLEN-1:0]   exu_wbu_data;  
wire [`ADDR_W-1:0] exu_wbu_pc;    
wire wr_addr_valid;
wire [`VADDR_W-1:0]wr_addr;
wire [7:0] wr_strb;
wire [127:0]wr_data;
wire wr_data_valid;
wire rd2_addr_valid;
wire [`VADDR_W-1:0]rd2_addr;
wire rd2_data_valid;
wire [127:0]rd2_data;
wire [31:0] exu_wbu_inst;
wire ctrl_wbu_flush;
wire csr_wbu_isClint;
wire [`EXCEPT:0] exu_wbu_exception;
wire             exu_wbu_wr_csr_en;
wire [11:0]      exu_wbu_wr_csr_addr;
wire [`XLEN-1:0] exu_wbu_wr_csr_data;
wire [11:0]      exu_csr_raddr;
wire [`XLEN-1:0] csr_exu_rdata;
wire             wbu_exu_wr_csr_en  ;
wire [11:0]      wbu_exu_wr_csr_addr;
wire [`XLEN-1:0] wbu_exu_wr_csr_data;
wire             wbu_wr_csr_en; 
wire [`EXCEPT:0] wbu_csr_exception;
wire [11:0]      wbu_wr_csr_addr; 
wire [`XLEN-1:0] wbu_wr_csr_data;  
wire             wbu_csr_commit;
wire clintEn       ;
wire clintInterrupt;
wire debug_selClint;
wire  [`VADDR_W-1:0] wbu_csr_pc  ;
wire  [31:0]         wbu_csr_inst;
// IMMU
wire                 fronted_mmu_trans_valid;
wire                 mmu_fronted_trans_ready;
wire [`VADDR_W-1:0]  fronted_mmu_trans_vaddr;
wire [`PADDR_W-1:0]  mmu_fronted_trans_paddr;
// DMMU
wire                 exu_mmu_trans_valid;
wire                 mmu_exu_trans_ready;
wire [`VADDR_W-1:0]  exu_mmu_trans_vaddr;
wire [`PADDR_W-1:0]  mmu_exu_trans_paddr;
// mem
wire rd_addr_valid;
wire [`PADDR_W-1:0]rd_addr;
wire rd_data_valid;
wire [127:0]rd_data;
// LSU 访问的接口
wire lsu_dcache_paddr_valid;
wire [`PADDR_W-1:0]lsu_dcache_paddr;
wire [7:0] lsu_dcache_strb;
wire lsu_dcache_wen;
wire lsu_dcache_invalidate;
wire [63:0] lsu_dcache_wdata;
wire  [63:0] dcache_lsu_rdata;
wire  dcache_lsu_data_valid;
// 下游访问接口 L2Cache 或内存
wire dcache_mem_addr_valid;
wire dcache_mem_wen;
wire [`PADDR_W-1:0] dcache_mem_addr;
wire [127:0] dcache_mem_wdata;
wire [7:0] dcache_mem_strb;
wire mem_dcache_data_valid;
wire [127:0] mem_dcache_rdata;

fronted frt(
  .clk      (clk),
  .rst_n    (rst_n),
  .boot_addr(boot_addr),
  // 流水线控制信号
  .ctrl_fronted_flush_i(ctrl_fronted_flush),
  .ctrl_baq_flush_i    (ctrl_baq_flush),
  .commit_fronted_invalidate_i(invalidateIcache),
  // commit 的 异常处理信号
  .commit_fronted_exception_i(commit_fronted_exception),
  .commit_fronted_exceptionPC_i(commit_fronted_exceptionPC),
  // bru 的 错误分支预测修正信号
  .bru_fronted_misPredict_i(bru_fronted_misPredict),
  .bru_fronted_valid_i(bru_fronted_valid),
  .bru_fronted_brunch_i(bru_fronted_brunch),
  .bru_fronted_JumpOldPC_i(bru_fronted_JumpOldPC),
  .bru_fronted_misPrePC_i(bru_fronted_misPrePC),
  // 输出到 IDU的 指令信号
  .fronted_idu_valid_o( fronted_idu_valid ),
  .idu_fronted_ready_i( idu_fronted_ready ),
  .fronted_idu_instr_o( fronted_idu_instr ),
  .fronted_idu_pc_o   ( fronted_idu_pc    ),
  .fronted_idu_pre_o  ( fronted_idu_pre   ),
  // MMU 预留接口 
  .fronted_mmu_trans_valid_o ( fronted_mmu_trans_valid ),
  .mmu_fronted_trans_ready_i ( mmu_fronted_trans_ready ),
  .fronted_mmu_trans_vaddr_o ( fronted_mmu_trans_vaddr ),
  .mmu_fronted_trans_paddr_i ( mmu_fronted_trans_paddr ),
  // 访存接口 Imem 只有读
  .fronted_mem_addr_valid_o ( fronted_mem_addr_valid ),
  .mem_fronted_data_valid_i ( mem_fronted_data_valid ),
  .fronted_mem_addr_o       ( fronted_mem_addr       ),
  .mem_fronted_data_i       ( mem_fronted_data       )
`ifdef PREDICT_PC
  ,
  // BAQ out
  .baq_bru_valid_o   ( baq_bru_valid ),
  .bru_baq_ready_i   ( bru_baq_ready ),
  .baq_bru_dout_o    ( baq_bru_dout  ) 
`endif
);

idu IDU(
  .clk (clk),
  .rst_n(rst_n),
  .ctrl_idu_flush_i(ctrl_idu_flush),
  // Fronted in
  .fronted_idu_valid_i      ( fronted_idu_valid ),
  .idu_fronted_ready_o      ( idu_fronted_ready ),
  .fronted_idu_instr_i      ( fronted_idu_instr ),
  .fronted_idu_vaddr_i      ( fronted_idu_pc    ),
  .fronted_idu_pre_i        ( fronted_idu_pre   ),
  // IDU 输出的寄存器信号
  .idu_isu_valid_o ( idu_isu_valid ),
  .isu_idu_ready_i ( isu_idu_ready ),
  .idu_isu_fu_o    ( idu_isu_fu    ),
  .idu_isu_op_o    ( idu_isu_op    ),
  .idu_isu_rs1_o   ( idu_isu_rs1   ),
  .idu_isu_rs2_o   ( idu_isu_rs2   ),
  .idu_isu_rd_o    ( idu_isu_rd    ),
  .idu_isu_rfwen_o ( idu_isu_rfwen ),
  .idu_isu_src1_o  ( idu_isu_src1  ),
  .idu_isu_src2_o  ( idu_isu_src2  ),
  .idu_isu_imm_o   ( idu_isu_imm   ),
  .idu_isu_pc_o    ( idu_isu_pc    ),
  .idu_isu_inst_o  ( idu_isu_inst  ),
  .idu_isu_pre_o   ( idu_isu_pre   )
);
wire [`XLEN-1:0] debug_a0;
isu ISU(
  .clk(clk),
  .rst_n(rst_n),
  .ctrl_isu_flush_i(ctrl_isu_flush),

  .idu_isu_valid_i ( idu_isu_valid  ),
  .isu_idu_ready_o ( isu_idu_ready  ),
  .idu_isu_fu_i    ( idu_isu_fu     ),
  .idu_isu_op_i    ( idu_isu_op     ),
  .idu_isu_rs1_i   ( idu_isu_rs1    ),
  .idu_isu_rs2_i   ( idu_isu_rs2    ),
  .idu_isu_rd_i    ( idu_isu_rd     ),
  .idu_isu_rfwen_i ( idu_isu_rfwen  ),
  .idu_isu_src1_i  ( idu_isu_src1   ),
  .idu_isu_src2_i  ( idu_isu_src2   ),
  .idu_isu_imm_i   ( idu_isu_imm    ),
  .idu_isu_pc_i    ( idu_isu_pc     ),
  .idu_isu_inst_i  ( idu_isu_inst   ),
  .idu_isu_pre_i   ( idu_isu_pre    ),
  /* common signal*/ 
  .isu_exu_valid_o ( isu_exu_valid ),
  .exu_isu_ready_i ( exu_isu_ready ),
  .isu_exu_op_o    ( isu_exu_op    ),
  .isu_exu_rd_o    ( isu_exu_rd    ),
  .isu_exu_rfwen_o ( isu_exu_rfwen ),
  .isu_exu_op1_o   ( isu_exu_op1   ),
  .isu_exu_op2_o   ( isu_exu_op2   ),
  .isu_exu_imm_o   ( isu_exu_imm   ),
  .isu_exu_pc_o    ( isu_exu_pc    ),
  .isu_exu_inst_o  ( isu_exu_inst  ),
  .isu_exu_pre_o   ( isu_exu_pre   ),
  /* fu enable signal */
  .alu_enable_o  ( alu_enable  ),
  .aluw_enable_o ( aluw_enable ),
  .bru_enable_o  ( bru_enable  ),
  .csr_enable_o  ( csr_enable  ),
  .lsu_enable_o  ( lsu_enable  ),
  /* exu hzard */
  .exu_isu_wen_i   ( exu_isu_wen  ),  
  .exu_isu_addr_i  ( exu_isu_addr ),  
  .exu_isu_data_i  ( exu_isu_data ),  
  /* wb hzard & wen regfile*/
  .wbu_isu_wen_i   ( wbu_isu_wen  ),  
  .wbu_isu_addr_i  ( wbu_isu_addr ),  
  .wbu_isu_data_i  ( wbu_isu_data ),

  .debug_a0(debug_a0)
);

exu EXU(
  .clk(clk),
  .rst_n(rst_n),
  .ctrl_exu_flush_i(ctrl_exu_flush),
  /* isu to exu signal */
  .isu_exu_valid_i ( isu_exu_valid  ),
  .exu_isu_ready_o ( exu_isu_ready  ),
  .alu_enable_i    ( alu_enable     ),
  .aluw_enable_i   ( aluw_enable    ),
  .bru_enable_i    ( bru_enable     ),
  .csr_enable_i    ( csr_enable     ),
  .lsu_enable_i    ( lsu_enable     ),
  .isu_exu_op_i    ( isu_exu_op     ),
  .isu_exu_rd_i    ( isu_exu_rd     ),
  .isu_exu_rfwen_i ( isu_exu_rfwen  ),
  .isu_exu_op1_i   ( isu_exu_op1    ),
  .isu_exu_op2_i   ( isu_exu_op2    ),
  .isu_exu_imm_i   ( isu_exu_imm    ),
  .isu_exu_pc_i    ( isu_exu_pc     ),
  .isu_exu_inst_i  ( isu_exu_inst   ),
  .isu_exu_pre_i   ( isu_exu_pre    ),
  /* exu bypass signal */
  .exu_isu_wen_o   ( exu_isu_wen  ),  
  .exu_isu_addr_o  ( exu_isu_addr ),  
  .exu_isu_data_o  ( exu_isu_data ),
  /* update ftonted */
  .bru_fronted_misPredict_o ( bru_fronted_misPredict ),
  .bru_fronted_valid_o      ( bru_fronted_valid      ),
  .bru_fronted_brunch_o     ( bru_fronted_brunch     ),
  .bru_fronted_JumpOldPC_o  ( bru_fronted_JumpOldPC  ),
  .bru_fronted_misPrePC_o   ( bru_fronted_misPrePC   ),
  /* exu to wbu */
  .exu_wbu_valid_o ( exu_wbu_valid ),
  .wbu_exu_ready_i ( wbu_exu_ready ),
  .exu_wbu_wen_o   ( exu_wbu_wen   ),
  .exu_wbu_rd_o    ( exu_wbu_rd    ),
  .exu_wbu_data_o  ( exu_wbu_data  ), 
  .exu_wbu_pc_o    ( exu_wbu_pc    ),
  .exu_wbu_inst_o  ( exu_wbu_inst  ),
  .exu_wbu_exception_o   ( exu_wbu_exception    ),
  .exu_wbu_wr_csr_en_o   ( exu_wbu_wr_csr_en    ),
  .exu_wbu_wr_csr_addr_o ( exu_wbu_wr_csr_addr  ),
  .exu_wbu_wr_csr_data_o ( exu_wbu_wr_csr_data  ),
  /* read csr port */
  .exu_csr_raddr_o ( exu_csr_raddr ),
  .csr_exu_rdata_i ( csr_exu_rdata ),
  /* wbu bypass csr write port */
  .wbu_exu_wr_csr_en_i   ( wbu_exu_wr_csr_en   ),
  .wbu_exu_wr_csr_addr_i ( wbu_exu_wr_csr_addr ),
  .wbu_exu_wr_csr_data_i ( wbu_exu_wr_csr_data ),
  // MMU
  .exu_mmu_trans_valid_o ( exu_mmu_trans_valid ),
  .mmu_exu_trans_ready_i ( mmu_exu_trans_ready ),
  .exu_mmu_trans_vaddr_o ( exu_mmu_trans_vaddr ),
  .mmu_exu_trans_paddr_i ( mmu_exu_trans_paddr ),
  /* MEM 端口*/
  .lsu_dcache_paddr_valid_o ( lsu_dcache_paddr_valid ),
  .lsu_dcache_paddr_o       ( lsu_dcache_paddr       ),
  .lsu_dcache_strb_o        ( lsu_dcache_strb        ),
  .lsu_dcache_wen_o         ( lsu_dcache_wen         ),
  .lsu_dcache_invalidate_o  ( lsu_dcache_invalidate  ),
  .lsu_dcache_wdata_o       ( lsu_dcache_wdata       ),
  .dcache_lsu_rdata_i       ( dcache_lsu_rdata       ),
  .dcache_lsu_data_valid_i  ( dcache_lsu_data_valid  ),
  .clintEn                  ( clintEn                ),
  .clintInterrupt           ( clintInterrupt         ),
  .debug_selClint           ( debug_selClint         )
`ifdef PREDICT_PC
  /* BAQ to bru */
  ,
  .baq_bru_valid_i          ( baq_bru_valid  ),
  .baq_bru_dout_i           ( baq_bru_dout   ),
  .bru_baq_ready_o          ( bru_baq_ready  )
`endif
);

wbu WBU(
  .clk(clk),
  .rst_n(rst_n),
  .ctrl_wbu_flush_i(ctrl_wbu_flush),
  .exu_wbu_valid_i ( exu_wbu_valid ),
  .wbu_exu_ready_o ( wbu_exu_ready ),
  .exu_wbu_wen_i   ( exu_wbu_wen   ),
  .exu_wbu_rd_i    ( exu_wbu_rd    ),
  .exu_wbu_data_i  ( exu_wbu_data  ), 
  .exu_wbu_pc_i    ( exu_wbu_pc    ),
  .exu_wbu_inst_i  ( exu_wbu_inst  ),
  .exu_wbu_exception_i   ( exu_wbu_exception   ),
  .exu_wbu_wr_csr_en_i   ( exu_wbu_wr_csr_en   ),
  .exu_wbu_wr_csr_addr_i ( exu_wbu_wr_csr_addr ),
  .exu_wbu_wr_csr_data_i ( exu_wbu_wr_csr_data ),
  /* wbu bypass signal & rf write enable signal*/
  .wbu_isu_wen_o   ( wbu_isu_wen  ),  
  .wbu_isu_addr_o  ( wbu_isu_addr ),  
  .wbu_isu_data_o  ( wbu_isu_data ),
  /* wbu csr bypass to exu */ 
  .wbu_exu_wr_csr_en_o   ( wbu_exu_wr_csr_en   ),
  .wbu_exu_wr_csr_addr_o ( wbu_exu_wr_csr_addr ),
  .wbu_exu_wr_csr_data_o ( wbu_exu_wr_csr_data ),
  /* wbu csr write */
  .wbu_wr_csr_en_o     ( wbu_wr_csr_en     ),
  .wbu_csr_exception_o ( wbu_csr_exception ),
  .wbu_wr_csr_addr_o   ( wbu_wr_csr_addr   ),
  .wbu_wr_csr_data_o   ( wbu_wr_csr_data   ),
  .wbu_csr_pc_o        ( wbu_csr_pc        ),
  .wbu_csr_inst_o      ( wbu_csr_inst      ),
  /* 特殊端口 */
  .wbu_csr_commit_o    ( wbu_csr_commit    ),
  .csr_wbu_isClint_i   ( csr_wbu_isClint   ),
  .debug_a0            ( debug_a0          ),
  .debug_selClint      ( debug_selClint    )
);
controlStatusRegisiter CSR(
  .clk   (clk  ),
  .rst_n (rst_n),
  // 同步写端口
  .wen   ( wbu_wr_csr_en ),
  .waddr ( wbu_wr_csr_addr ),
  .wdata ( wbu_wr_csr_data ),
  // 读端口
  .raddr ( exu_csr_raddr ),
  .rdata ( csr_exu_rdata ),
  // 特殊端口
  .wbu_csr_commit_i    ( wbu_csr_commit             ),
  .wbu_csr_exception_i ( wbu_csr_exception          ),
  .wbu_csr_pc_i        ( wbu_csr_pc                 ),
  .wbu_csr_inst_i      ( wbu_csr_inst               ),
  .clintEn             ( clintEn                    ),
  .clintInterrupt      ( clintInterrupt             ),
  .commit_flush        ( commit_fronted_exception   ),
  .commit_addr         ( commit_fronted_exceptionPC ),
  .commit_invalidate   ( invalidateIcache           ),
  .csr_wbu_isClint_o   ( csr_wbu_isClint            )
);
pipelineControl PipeCtrl(
  .rst_n(rst_n),
  // flush request
  .ex_br_flush_i(bru_fronted_valid && bru_fronted_misPredict),
  .csr_commit_flush_i(commit_fronted_exception  ),
  // flush signal
  .ctrl_fronted_flush_o(ctrl_fronted_flush),
  .ctrl_idu_flush_o    (ctrl_idu_flush    ),
  .ctrl_isu_flush_o    (ctrl_isu_flush    ),
  .ctrl_exu_flush_o    (ctrl_exu_flush    ),
  .ctrl_wbu_flush_o    (ctrl_wbu_flush    ),
  .ctrl_baq_flush_o    (ctrl_baq_flush    )
);
mmu MMU(
  .clk  (clk  ),
  .rst_n(rst_n),
  // system message
  
  // I MMU 
  .fronted_mmu_trans_valid_i ( fronted_mmu_trans_valid ),
  .mmu_fronted_trans_ready_o ( mmu_fronted_trans_ready ),
  .fronted_mmu_trans_vaddr_i ( fronted_mmu_trans_vaddr ),
  .mmu_fronted_trans_paddr_o ( mmu_fronted_trans_paddr ),
  // D MMU
  .exu_mmu_trans_valid_i ( exu_mmu_trans_valid ),
  .mmu_exu_trans_ready_o ( mmu_exu_trans_ready ),
  .exu_mmu_trans_vaddr_i ( exu_mmu_trans_vaddr ),
  .mmu_exu_trans_paddr_o ( mmu_exu_trans_paddr )
  // Dcache Access

);
DcacheHasMmio Dcache(
  .clk(clk),
  .rst_n(rst_n),
  .invalidate(1'b0),
  // LSU 访问的接口
  .lsu_dcache_addr_valid_i (lsu_dcache_paddr_valid),
  .lsu_dcache_addr_i       (lsu_dcache_paddr      ),
  .lsu_dcache_strb_i       (lsu_dcache_strb       ),
  .lsu_dcache_wen_i        (lsu_dcache_wen        ),
  .lsu_dcache_invalidate_i (lsu_dcache_invalidate ),
  .lsu_dcache_wdata_i      (lsu_dcache_wdata      ),
  .dcache_lsu_rdata_o      (dcache_lsu_rdata      ),
  .dcache_lsu_data_valid_o (dcache_lsu_data_valid ),
  // 下游访问接口 L2Cache 或内存
  .dcache_mem_addr_valid_o (dcache_mem_addr_valid ),
  .dcache_mem_wen_o        (dcache_mem_wen        ),
  .dcache_mem_addr_o       (dcache_mem_addr       ),
  .dcache_mem_wdata_o      (dcache_mem_wdata      ),
  .dcache_mem_strb_o       (dcache_mem_strb       ),
  .mem_dcache_data_valid_i (mem_dcache_data_valid ),
  .mem_dcache_rdata_i      (mem_dcache_rdata      )
);

user2AXI MemBridge(
  .clk(clk),
  .rst_n(rst_n),

  .icache_mem_addr_valid_i ( fronted_mem_addr_valid ),
  .icache_mem_addr_i       ( fronted_mem_addr       ),
  .mem_icache_data_valid_o ( mem_fronted_data_valid ),
  .mem_icache_data_o       ( mem_fronted_data       ),

  .dcache_mem_addr_valid_i (dcache_mem_addr_valid ),
  .dcache_mem_wen_i        (dcache_mem_wen        ),
  .dcache_mem_addr_i       (dcache_mem_addr       ),
  .dcache_mem_wdata_i      (dcache_mem_wdata      ),
  .dcache_mem_strb_i       (dcache_mem_strb       ),
  .mem_dcache_data_valid_o (mem_dcache_data_valid ),
  .mem_dcache_rdata_o      (mem_dcache_rdata      ),
 
  .axi_aw_ready      (axi_aw_ready),       
  .axi_aw_valid      (axi_aw_valid),   
  .axi_aw_bits_addr  (axi_aw_addr ),   
  .axi_aw_bits_prot  (axi_aw_prot ),   
  .axi_aw_bits_id    (axi_aw_id   ),
  .axi_aw_bits_user  (axi_aw_user ),     
  .axi_aw_bits_len   (axi_aw_len  ),      
  .axi_aw_bits_size  (axi_aw_size ),
  .axi_aw_bits_burst (axi_aw_burst),
  .axi_aw_bits_lock  (axi_aw_lock ),   
  .axi_aw_bits_cache (axi_aw_cache),   
  .axi_aw_bits_qos   (axi_aw_qos  ),   
  
  .axi_w_ready     (axi_w_ready) ,  
  .axi_w_valid     (axi_w_valid) ,
  .axi_w_bits_data (axi_w_data ) ,   
  .axi_w_bits_strb (axi_w_strb ) ,   
  .axi_w_bits_last (axi_w_last ) ,   
  
  .axi_b_ready     (axi_b_ready ),
  .axi_b_valid     (axi_b_valid ),
  .axi_b_bits_resp (axi_b_resp  ),  
  .axi_b_bits_id   (axi_b_id    ),
  .axi_b_bits_user (axi_b_user  ),
  
  .axi_ar_ready      (axi_ar_ready ),
  .axi_ar_valid      (axi_ar_valid ),
  .axi_ar_bits_addr  (axi_ar_addr  ),
  .axi_ar_bits_prot  (axi_ar_prot  ),
  .axi_ar_bits_id    (axi_ar_id    ),
  .axi_ar_bits_user  (axi_ar_user  ),
  .axi_ar_bits_len   (axi_ar_len   ),
  .axi_ar_bits_size  (axi_ar_size  ),
  .axi_ar_bits_burst (axi_ar_burst ),
  .axi_ar_bits_lock  (axi_ar_lock  ),
  .axi_ar_bits_cache (axi_ar_cache ),
  .axi_ar_bits_qos   (axi_ar_qos   ),

  .axi_r_ready     (axi_r_ready ),
  .axi_r_valid     (axi_r_valid ),
  .axi_r_bits_resp (axi_r_resp  ),
  .axi_r_bits_data (axi_r_data  ),
  .axi_r_bits_last (axi_r_last  ),
  .axi_r_bits_id   (axi_r_id    ),
  .axi_r_bits_user (axi_r_user  ) 
);
  
endmodule